In Intermediate Factorio Lab 3 (IFL-3), we define a mechanism to allow some specified Train T(M) to stop at train stop S(N) and then continue to an arbitrarily specified train stop S(O). This is accomplished by providing information on S(O) via signal U and by detecting when a has arrived at a train stop via the read stopped train option. IFL-3 provides the barebones for achieving this; practical applications would require further conditions to be met before returning or sending a train back such as the loading of inventory up to a specified level, a certain amount of time, etc.
Motivation
IFL-3 is relatively sophisticated when compared with Labs 1 and 2. The payoff, though, is a framework with the capability to automate delivery to various sites with differing payloads using circuit network conditions. The techniques presented in IFL-3 can also be used to offer a ‘homing’ mechanism back to the construction site if there are multiple construction sites. E.g.: A chest runs low on solar panels at S(N = X), an order for more solar panels is placed and T(M = 1) can be automatically instructed to go back to HQ, pick up the goods, and return to S(N = X) for automatic delivery into providers that woudl supply buffer chests and make their contents available to construction robots at the site.
Significant Considerations:
– Signal separation
– Signal use / reuse / conversion
– memory cell design
Major Challenges:
– Signal receivers and transmitters are stateless. A memory cell is used to store information on the next hop. There are various memory cell designs; we employ a resetable memory cell to hold information on the next hop.
– Trains other than the desired T(M) may arrive at train stop S(N) while T(M) is in transit. Therefore, we must find a way of identifying when T(M) is at S(N). Comparing identical signals has a learning curve initially. When comparing identical signals some options are:
* identity (T = T) which requires signal conversion since identical signals are added together regardless of wire colors.
* zero property ( T + -T = 0 ). This may seem like the easiest approach, unfortunately, T = 0 results in bistability. If there are no T present, T = 0 :=> TRUE. If signal isolation can be guaranteed, it might be possible to use a SPECIAL signal (Anything) to overcome this bi-stability. For IFL-3, this is too convoluted to execute.
In the end, identity is the least convoluted method. Train stops will ‘read stopped train’ and transmit that train’s ID on signal L. Using a separate signal (instead of T, which is already reserved for the Train ID) is necessary or else the signals SUM together and neither condition is met. The ID is then algebreically negated pulsed via a rising edge detector which is necessary – in this case the rising edge detector identifies when a train has stopped; a falling edge detector would detect when a train has left.. L is then compared with T for equality and all signals are passed through a filter preventing the transmission of L back into the network which happens when any train OTHER than T(M) stops at S(N). It’s important to note that L should be removed from downstream logic which is accomplished via a synchronous negation of L which happens in sync with the equality check and the afformentioned filter.
* When T = L, instructions are sent to the global network and the memory cell that holds the next hop is cleared. We pass the signals through an ANYTHING != 0 filter which shoots R(1) that resets the memory cell.
Instructions: Instructions will focus on understanding necessary circuitry required to make this project come together. No major updates to the supporting infrastructure are required if IFL-2 has already been implemented.
1. Most upgrades were conducted in IFL-2. All participating stations should have Read Stopped Train turned on to L.
2. Circuit logic will be re-ordered to accommodate the added sophistication incurred as a result of the objective requirements. Clear All combinators off the board!
3.a INGRESS Logic – this logic accepts signals from global network
– (T-Filter) D1: T != 0 :=> T (IFF T is non-zero, pass T)
(T Sync bit) A1: T * 1 :=> T (T Identity – 1 tick sync bit)
– (S-Filter) D2: S = N :=> Ev. (Pass All signals IFF S = N)
(U-Conv.) A2: U * 1 :=> S (Convert U back to S for Next Hop when S = N).
A3: T * 1 :=> T (Send T When S = N) sa
– (S-Comp.) D3: S = 0 :=> S(1) (S-comparator for bistability)
D4: S = N :=> S(1)
A4: S * N :=> S (IF S = 0 OR S = N THEN S = N)
– (Memcell) D5: R = 0 :=> Ev. (Pass all if R = 0. Reset when R != 0)
3.b INTERNAL / EGRESS Logic. This logic accepts signals from the train stop.
– (L-Neg) A5: T * -1 :=> L (returns as additive inverse of L)
– (All-Neg) A7: Ea. * -1 :=> Ea. (When input with A4, used as a ‘pulser’ – pulser is necessary; even with pulsed signals, T(M) spends at least 4 ticks at S(N))
– (L-Filter) A7: L * -1 :=> L (Used in sync with T-L Check.)
– (T-L Chck.) D6: T = L :=> Ev. (Pass all signals IFF T = L; wired to Memcell input. Green out to global, red out to Mem reset)
– (NOT L Gate) D7: L = 0 :=> Ev. (only passes traffic to downstream logic IFF L = 0. Prevents L from tripping Mem Reset when T != M at S(N))
– (Mem reset) D7: An. != 0 :=> R(1) (Send R if Anything !=0)
4. Test away!
I would like to add some GIFs in here so I don’t have to upload a video to present some functionality. Please reach out with advice on this!
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